Loading src/core/or/circuitbuild.c +1 −2 Original line number Diff line number Diff line Loading @@ -1289,8 +1289,7 @@ circuit_finish_handshake(origin_circuit_t *circ, * don't seem able to do it, so there is some magic way that hops can * still get added. Perhaps some cases of circuit pre-build that change * purpose? */ static ratelim_t cc_path_limit = RATELIM_INIT(600); log_fn_ratelim(&cc_path_limit, LOG_NOTICE, LD_CIRC, log_info(LD_CIRC, "Unexpected path length %d for exit circuit %d, purpose %d", circ_len, circ->global_identifier, TO_CIRCUIT(circ)->purpose); Loading Loading
src/core/or/circuitbuild.c +1 −2 Original line number Diff line number Diff line Loading @@ -1289,8 +1289,7 @@ circuit_finish_handshake(origin_circuit_t *circ, * don't seem able to do it, so there is some magic way that hops can * still get added. Perhaps some cases of circuit pre-build that change * purpose? */ static ratelim_t cc_path_limit = RATELIM_INIT(600); log_fn_ratelim(&cc_path_limit, LOG_NOTICE, LD_CIRC, log_info(LD_CIRC, "Unexpected path length %d for exit circuit %d, purpose %d", circ_len, circ->global_identifier, TO_CIRCUIT(circ)->purpose); Loading