Loading src/or/main.c +0 −1 Original line number Diff line number Diff line Loading @@ -224,7 +224,6 @@ set_buffer_lengths_to_zero(tor_socket_t s) } #endif /** Return 1 if we have successfully built a circuit, and nothing has changed * to make us think that maybe we can't. */ Loading src/or/scheduler.c +1 −0 Original line number Diff line number Diff line Loading @@ -706,3 +706,4 @@ scheduler_set_watermarks(uint32_t lo, uint32_t hi, uint32_t max_flush) sched_q_high_water = hi; sched_max_flush_cells = max_flush; } Loading
src/or/main.c +0 −1 Original line number Diff line number Diff line Loading @@ -224,7 +224,6 @@ set_buffer_lengths_to_zero(tor_socket_t s) } #endif /** Return 1 if we have successfully built a circuit, and nothing has changed * to make us think that maybe we can't. */ Loading
src/or/scheduler.c +1 −0 Original line number Diff line number Diff line Loading @@ -706,3 +706,4 @@ scheduler_set_watermarks(uint32_t lo, uint32_t hi, uint32_t max_flush) sched_q_high_water = hi; sched_max_flush_cells = max_flush; }